11TH IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS
San José, Costa Rica
February 26-28, 2020
The Iberchip workshop provides an annual forum to academic and industrial researchers from Iberoamerican countries in which to exchange experiences, share knowledge, and establish relations to foster the development of activities related to the field of microelectronics. Special emphasis is put in the improvement of education and training, and in the promotion of joint cooperative projects.
The 26th edition will take place in San José, the capital of Costa Rica. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO), where major government institutions, public universities, and industry converge in a metropolitan area with over two million people. The west urban area of San José hosts a vibrant business environment, encompassing the operation of more than 200 high-tech companies in fields such as electronics, software, and biomedical applications.Call For Papers
San José, Costa Rica
February 26-28, 2020
The PhD Research in Microelectronics and Electronics Conference in Latin America (PRIME-LA) is a conference where PhD students and post-docs with less than one-year post-PhD experience can present their research results and network with experts from industry, academia and research.
The third edition will take place in San José, the capital of Costa Rica. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO), where major government institutions, public universities, and industry converge in a metropolitan area with over two million people. The west urban area of San José hosts a vibrant business environment, encompassing the operation of more than 200 high-tech companies in fields such as electronics, software, and biomedical applications.Call For Papers
LASCAS is the flagship conference of the IEEE Circuits and Systems
Society in Latin America. Since its first edition in 2010, LASCAS provides a high-quality exchange
and networking forum for researchers, professionals, and students, gathering an international
audience with experts from all over the world. This event is a space where the CAS community can
present new concepts and innovative approaches, learn about new trends and solutions, and receive
feedback from specialists in diverse fields.
The 11th edition will take place in San José, the capital of Costa Rica. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO), where major government institutions, public universities, and industry converge in a metropolitan area with over two million people. The west urban area of San José hosts a vibrant business environment, encompassing the operation of more than 200 high-tech companies in fields such as electronics, software, and biomedical applications.
Christian Schuster (S'98 - M'00 - SM'05) received the Diploma degree in physics from the University of Konstanz, Germany, in 1996, and the Ph. D. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in 2000. Since 2006 he is full professor and head of the Institute of Electromagnetic Theory at the Hamburg University of Technology (TUHH), Germany. Prior to that he was with the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he was involved in high-speed optoelectronic package and backplane interconnect modeling and signal integrity design for new server generations. His currents interests include signal and power integrity of digital systems, multiport measurement and calibration techniques, and development of electromagnetic simulation methods for communication electronics. Dr. Schuster received IEEE Transactions on EMC Best Paper Awards in 2001 and 2015, IEEE Transactions on CPMT Best Paper Awards in 2012 and 2016, IEC DesignCon Paper Awards in 2005, 2006, 2010, 2017 and 2018, three IBM Research Division Awards between 2003 and 2005, and IBM Faculty Awards in 2009 and 2010. He is a member of the German Physical Society (DPG) and several technical program committees of international conferences on signal and power integrity, and electromagnetic compatibility. He was serving as a Distinguished Lecturer for the IEEE EMC Society in the period 2012-2013, as a member of the Board of Directors of the EMC Society in 2015, and is currently chair of the German IEEE EMC Chapter and Associate Editor for the IEEE Transactions on EMC.
Talk: Artificial Neural Networks for EMC Engineering
Abstract: Artificial Neural Networks – in short: ANNs – are one of the many methods used nowadays in Machine Learning (ML). Their fundamental development has spanned many decades and they have found widespread use in such areas as image and speech recognition as well as autonomous driving. Despite this success ANNs have not been applied routinely to complex engineering task such as guaranteeing the Electromagnetic Compatibility (EMC) of electrical and electronic components and systems. In this talk – a after a short, layman’s introduction into ML and ANNs – we will look in some detail at the current state of art in the application of ANNs to EMC engineering including an example from power delivery network design that we worked recently on at TUHH. A personal outlook will conclude the presentation
Dr. Shamma's research deals with issues in cognitive neuroscience, computational neuroscience, neuromorphic engineering, and the development of microsensor systems for experimental research and neural prostheses. Primary focus has been on studying the principles underlying the processing and recognition of complex sounds (speech and music) in the auditory system, and specifically the role of attention and rapid plasticity in facilitating these functions. Research projects involve single-unit behavioral neurophysiology and 2-photon imaging of the auditory cortex, and its interactions with higher cortical centers such as the prefrontal cortex and secondary auditory areas. Signal processing algorithms inspired by these experiments are developed and applied in a variety of systems such as speech and voice recognition, diagnostics in industrial manufacturing, and underwater acoustics. Other research interests include the development of microelectrode arrays for recording and stimulation of neural signals, analog VLSI implementations of auditory processing algorithms, and development of robotic systems for the detection and tracking of multiple simultaneous sound sources.
Talk: How Auditory Cortical Representations Inspire Speech and Music Processing Systems.
Abstract: The brain is a complex information processing system that is difficult to comprehend following any one experimental and theoretical approach. Instead, it has yielded fascinating insights only when diverse techniques were applied to its study. The remarkable capabilities of the brain has also inspired enormous interest in replicating them in Neuromorphic hardware and software so as both to derive insights into and also benefit from replicating its functionality. In this talk, I will address these topics focusing on the case of the auditory system and its applications to audio processing and recognition of speech, music, and the relevance of these applications to the understanding of language and music in the brain.
Wouter A. Serdijn (M'98, SM'08, F'11) was born in Zoetermeer ('Sweet Lake City'), the Netherlands, in 1966. He received the M.Sc. (cum laude) and Ph.D. degrees from Delft University of Technology, Delft, The Netherlands, in 1989 and 1994, respectively. Currently, he is a full professor in bioelectronics at Delft University of Technology, where he heads the Section Bioelectronics, and a visiting honorary professor at University College London, in the Analog and Biomedical Electronics group. His research interests include integrated biomedical circuits and systems for biosignal conditioning and detection, neuroprosthetics, transcutaneous wireless communication, power management and energy harvesting as applied in, e.g., hearing instruments, cardiac pacemakers, cochlear implants, neurostimulators, portable, wearable, implantable and injectable medical devices and electroceuticals. He is co-editor and co-author of the books Analog IC Design Techniques for Nanopower Biomedical Signal Processing (River Publishers 2016), Design of Efficient and Safe Neural Stimulators - a multidisciplinary approach (Springer, 2016), EMI-Resilient Amplifier Circuits (Springer 2013), Ultra Low-Power Biomedical Signal Processing: an analog wavelet filter approach for pacemakers (Springer, 2009), Circuits and Systems for Future Generations of Wireless Communications (Springer, 2009), Power Aware Architecting for data dominated applications (Springer, 2007), Adaptive Low-Power Circuits for Wireless Communications (Springer, 2006), Research Perspectives on Dynamic Translinear and Log-Domain Circuits (Kluwer, 2000), Dynamic Translinear and Log-Domain Circuits (Kluwer, 1998) and Low-Voltage Low-Power Analog Integrated Circuits (Kluwer, 1995). He authored and co-authored 8 book chapters, 4 patents and more than 300 scientific publications and presentations. He teaches Circuit Theory, Analog Integrated Circuit Design, Analog CMOS Filter Design, Active Implantable Biomedical Microsystems and Bioelectronics. He received the Electrical Engineering Best Teacher Award in 2001, in 2004 and in 2015. He has served, a.o., as General Co-Chair for IEEE ISCAS 2015 and for IEEE BioCAS 2013, Technical Program Chair for IEEE BioCAS 2010 and for IEEE ISCAS 2010, 2012 and 2014, as a member of the Board of Governors (BoG) of the IEEE Circuits and Systems Society ( 2006—2011), as chair of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems society, and as Editor-in-Chief for IEEE Transactions on Circuits and Systems—I: Regular Papers (2010—2011). Currently, he is the chair of the Steering Committee and an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems (T-BioCAS). Wouter A. Serdijn is an IEEE Fellow, an IEEE Distinguished Lecturer and a mentor of the IEEE. In 2016, he received the IEEE Circuits and Systems Society Meritorious Service Award.
Talk Title: The Medicine of the Future You'll Take Only Once, and it is Bioelectronic Abstract: The 21st century will be the century in which we will unravel the intricacies of the brain and the rest of our nervous system and in which we will learn how to interact with our electrochemical mainframe better by means of electricity, light or ultrasound. Tiny electronic devices will give us back lost senses, lost control, bypass lesions and treat an unprecedented range of brain disorders, thereby bringing back quality of life to the deaf, the blind, the paralyzed and the mentally disturbed. This talk will address how these ‘bioelectronic medicines’ do this, what they look like and which future circuit and system developments are needed to make them a reality. We will discuss their constraints on size, their energy challenge, their adherence to the body and their security aspects. We will also discuss how to make them truly personalized, so that they gracefully adapt to your therapeutic needs and you truly will feel better.
Motorola Endowed Professor in Integrated Circuits. Director, USAID PCASE Center on Energy. Director, NSF Connection One Center. Professor, School of Electrical, Computer, and Energy Engineering Ira. A. Fulton Schools of Engineering, Arizona State University Ph.D., electrical and computer engineering, Washington State University, 1987. Dr. Kiaei has been with ASU since January 2001. He is a professor and Motorola Endowed professor and chair in analog and RF integrated circuits. He is the director of the USAID-funded U.S.A & Pakistan Centers for Advanced Studies in Energy program (USPCAS-E (https://uspcase.asu.edu/). He is also the director of NSF Connection One research center with a focus on integrated communication system. Dr. Kiaei was the associate dean of research at the Ira A. Fulton Schools of Engineering from 2009 to 2102. From 1993 to 2001, he was a senior member of technical staff with the Wireless Technology Center and Broadband Operations at Motorola where he was responsible for the development of RF and transceiver integrated circuits, GPS RF IC and digital subscriber lines (DSL) transceivers. Kiaei was an associate professor at Oregon State University from 1987 to 1993. He was the co-director of the industry-university center for the Design of Analog/Digital ICs (CDADIC). He has published over 150 journal and conference papers and holds several patents. His academic and research interests are in Energy, wireless system (1G to 5G), RF, and Mixed-Signal. His research projects are funded by a large number of industrial sponsors and federal funding agencies. Dr. Kiaei is an IEEE Fellow, and has been the chair and on the technical program committee of several IEEE conferences including RFIC, MTT, ISCAS and other international conferences.
Talk: Overview of 5G Radio Systems, Requirements, Challenges, and Research Areas.
Abstract: As demand grows for wireless connectivity in many applications including autonomous vehicles, artificial intelligence, telemedicine and virtual reality will have a dominate role in 5G. 5G will be delivering higher data throughput, extremely low latency speeds up to 100 times faster than 4G. This talk will give an overview of the 5G technology, standards, and challenges for RF and wireless transceivers. The talk will focus on the RF architecture and transceivers for the 5G RF front-end.
Jesús A. del Alamo is Professor of Electrical Engineering and Director of the Microsystems Technology Laboratories at Massachusetts Institute of Technology. He obtained a Telecommunications Engineer degree from the Polytechnic University of Madrid and MS and PhD degrees in Electrical Engineering from Stanford University. From 1985 to 1988 he was with NTT LSI Laboratories in Atsugi (Japan) and since 1988 he has been with the Department of Electrical Engineering and Computer Science of MIT where he is at the present time the Donner Professor. His current research interests are centered on nanoelectronics based on compound semiconductors for future logic, communications and power management applications. Prof. del Alamo was an NSF Presidential Young Investigator. He is a member of the Royal Spanish Academy of Engineering and Fellow of the IEEE and the APS. He has received the Intel Outstanding Researcher Award, the SRC Technical Excellence Award, and the IEEE EDS Education Award. He currently serves as Editor-in-Chief of IEEE Electron Device Letters.
Talk: Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs.
In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, III-V compound semiconductors, in particular InGaAs, have received a great deal of attention as possible alternatives. Sub-10 nm CMOS applications require high-aspect ratio 3D transistors with a fin or nanowire geometry. The enhanced degree of channel charge control of advanced 3D designs allows for transistor size scaling to extremely small dimensions. At MIT, we are investigating the prospects of nanoscale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs for future logic applications. We are pursuing a top-down fabrication approach. Towards this goal, we have developed Reactive Ion Etching technology for In-containing III-V compounds that yields high aspect ratio structures with vertical and smooth sidewalls. We have also perfected digital etch to controllably thin down fins and vertical nanowires to below 10 nm width/diameter with high yield. Using these technologies, we have demonstrated InGaAs VNW MOSFETs and FinFETs with sub-10 nm critical dimensions and record electrical characteristics. More recently, we have developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We have shown that the in-situ integration of TALE with atomic layer deposition of the gate dielectric allows the fabrication of the gate stack without exposure to air. This approach has yielded the most scaled InGaAs FinFETs to date with sub-3 nm fin widths and record ON-and OFF-state characteristics. Our nanoscale device studies reveal OFF-state leakage current, mobility degradation and gate oxide trapping as major stumbling blocks for future use of InGaAs 3D transistors in logic applications. This talk will review these and other problematic issues with III-V CMOS and discuss possible solutions.
Vida Ilderem is vice president of Intel Labs and director of the Integrated Platform Research at Intel Corporation. The research lab focuses on deep integration on highly integrated platform-on-chip architectures as well as digital, analog and physical design factors. Prior to joining Intel, Ilderem served as vice president of Systems and Technology Research at Motorola's Applied Research and Technology Center where she led research efforts that focused on delivering solutions for the next generation of communication and interaction technologies and integrated systems. She has also held the position of vice president of Physical & Digital Realization with focus on visual, computational and physical technologies, and served as director of RF/IF silicon technologies within Motorola's Semiconductor Products Sector.
Ilderem holds 27 issued patents and has been featured in numerous publications. She is a recipient of the Motorola's Distinguished Innovator Award. Ilderem holds bachelor's degrees in electrical engineering and physics from Fresno State and a master's degree and doctorate degree in electrical engineering from the Massachusetts Institute of Technology (MIT).
David Atienza Alonso received his MSc and PhD degrees in Computer Science and Engineering from Complutense Univ. of Madrid (UCM), Spain, and IMEC, Belgium, in 2001 and 2005, respectively. Currently he is an associate professor of electrical and computer engineering, and head of the Embedded Systems Laboratory (ESL) at the Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland. His research interests include system-level design methodologies for high-performance multi-processor system-on-chip (MPSoC) and low-power Internet-of-Things (IoT) systems, including new 2-D/3-D thermal-aware design for MPSoCs and many-core servers, ultra-low power edge AI architectures for wireless body sensor nodes and smart embedded systems, HW/SW reconfigurable systems, dynamic memory optimizations, and network-on-chip design. He is a co-author of more than 300 publications in peer-reviewed international journals and conferences, several book chapters, and eight licensed U.S. patents in these fields. He has earned several best paper awards and he is (or has been) an Associate Editor of IEEE TC, IEEE D&T, IEEE T-TCAD, IEEE TETC, IEEE T-SUSC and Elsevier Integration. He was the Technical Programme Chair of IEEE/ACM DATE 2015 and General Programme Chair of IEEE/ACM DATE 2017. Dr. Atienza received the DAC Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He is an IEEE Fellow and an ACM Distinguished Member. He has earned several best paper awards and he is (or has been) an Associate Editor of IEEE TC, IEEE D&T, IEEE T-TCAD, IEEE TETC, IEEE T-SUSC and Elsevier Integration. He was the Technical Programme Chair of IEEE/ACM DATE 2015 and General Programme Chair of IEEE/ACM DATE 2017. Dr. Atienza received the DAC Under-40 Innovators Award in 2018, the IEEE TCCPS Mid-Career Award in 2018, an ERC Consolidator Grant in 2016, the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012, and a Faculty Award from Sun Labs at Oracle in 2011. He is an IEEE Fellow and an ACM Distinguished Member.
Talk: Energy-Scalable Many-Core Servers: Follow Your Brain!
Abstract: Continuous advances in manufacturing technologies are enabling the development of more powerful and compact high-performance computing (HPC) servers made of many-core processing architectures. However, this soaring demand for computing power in the last years has grown faster than semiconductor technology evolution can sustain, and has produced as collateral undesirable effect a surge in power consumption and heat density in these new HPC servers, which result on significant performance degradation. In this talk, Prof. Atienza will advocate to completely revise the current practices to design HPC server architectures. In particular, inspired by the mammalian brain, I propose to design a disruptive three-dimensional (3D) computing server architecture that overcomes the prevailing worst-case power and cooling provisioning paradigm for servers. This new 3D server design champions a new system-level thermal modeling and machine learning based task assignment (developed in cooperation with Facebook), which can be used by novel proactive energy controllers for detailed heat and energy management in many-core HPC servers, thanks to micro-scale liquid cooling. Then, it will be shown the impact of new near-threshold computing architectures on many-core server design. Finally, I will explain how we can integrate new on-chip microfluidic fuel cell networks to enable energy-scalability in future generations of many-core HPC servers targeting the next-generation of Exascale computing, thanks to the new PowerCool and Gem5-X open-source multi-core architectural simulators.
Naysen Robertson began his career in the Business Critical Systems unit at HP in 1999. Working as a hardware engineer and later architect, Naysen's technical leadership helped deliver several Itanium and x86 enterprise-class systems, such as the award winning ProLiant DL980 scale-up, 8-skt server. Naysen currently serves as a Master technologist in the HPE Silicon Design Lab where he is sought after for his broad expertise in systems architecture and his deep knowledge in the field of FPGA design and ASIC emulation. He synthesizes his experience, skillsets and leadership to solve the pressing challenges of pre-silicon design validation. Naysen has a BS in CPE from California State University of Sacramento, and he holds several patents in areas such as NUMA architecture and embedded system manageability.
Talk: An approach to generational, pre-silicon SoC/ASIC Prototyping Abstract: A majority of organizations developing application-specific integrated circuit (ASIC) designs rely upon some form of pre-silicon hardware to accelerate verification of their solutions beyond software based simulation/emulation. Software simulation of silicon design is flexible and relatively low-cost, but executing micro-code and long dwell simulation is time-prohibitive and incapable of capturing the parallel nature of synchronous designs. This leads to verification misses at synchronization thresholds and other temporal flaws introduced in the register transfer level (RTL) model. There is a continuum of hardware-based Design Verification solutions that ranges from simple, off-the-shelf printed circuit assembly (PCA) cards with a programmable device to the high-cost, high-complexity emulation boxes available from our premier Electronic Design Automation (EDA) vendors. At HPE, our approach to enabling an ASIC equivalent prototyping solution that is cost, effort, and capability optimized involves the use of generational, custom, field programmable gate array (FPGA)-based PCAs designed to load our Baseboard Management Controller (BMC) ASIC design, execute WiP Firmware, and integrate within current generation server platforms that are modified to detect and seamlessly connect previous or current generation ASIC }add-in cards as well as next-generation FPGA-based cards to the host system. This presentation gives an overview of this approach to FPGA accelerated ASIC validation with an analysis of the trade-offs with alternative approaches.
Kevin Boyum received his BSEE degree from the Virginia Military Institute in 1989 and his MSEE degree from the Air Force Institute of Technology in 1993, and served as an Electrical Engineer performing research and development in the United States Air Force from 1989 through 1996. Joining Hewlett Packard's Enterprise Server and Technology Lab in 1997, he developed state of the art data capture hardware for the jointly developed HP / Intel Itanium processor chipset and then architected management and storage solutions for HP's Itanium-based servers and for HPE's Synergy platform. In 2015 Kevin was selected as the hardware engineering lead for HP Labs' project The Machine, HP's first prototype for the Memory Driven Compute architecture, and following the successful technology demonstration has continued as a systems architect in HPE's Silicon Design Lab. Kevin has authored and co-authored 10 patents and his profession interests include embedded systems design and programming, computer systems architecture, and machine learning.
Talk: Memory-Driven Computing. Big Data is here, growing, and sourcing tremendous unrealized business opportunities! Yet, as the number of data sources and the amount of data gathered continues to increase exponentially, transistor scaling and the corresponding increase in compute ability has slowed dramatically, reducing our ability to interact with this mounting data in a meaningful timeframe. Hewlett Packard Enterprise has met this challenge with an entirely new approach called Memory-Driven Computing. Designed specifically for Big Data, Memory-Driven Computing turns traditional computer architecture on its head by making memory central to the system, rather than processors. This presentation explores the fundamental principles and building blocks of Memory-Driven Computing and how it differs from conventional design, then highlights examples of the incredible speedups achieved so far on real-world workloads.
Michelle J. Johnson, Ph.D., is currently Assistant professor of physical medicine and rehabilitation at the University of Pennsylvania. She has a secondary appointment as an Assistant professor in Bioengineering and is a member of the Mechanical Engineering and Applied Mechanics graduate group. She has a Bachelors of Science in Mechanical Engineering and Applied Mechanics from the University of Pennsylvania and a PhD in Mechanical Engineering, with an emphasis in mechatronics, robotics, and design, from Stanford University. She completed a NSF-NATO post-doctoral fellowship at the Advanced Robotics Technology and Systems Laboratory at the Scuola Superiore Sant’Anna in Italy. She directs the Rehabilitation Robotic Research and Design Laboratory located at the Pennsylvania Institute of Rehabilitation Medicine at the University of Pennsylvania, School of Medicine. The lab is also affiliated with the General Robotics Autameted Sensing Perception (GRASP) Lab.
Dr. Johnson’s lab specializes in the design, development, and therapeutic use of novel, affordable, intelligent robotic assistants for rehabilitation in high and low-resource environments with an emphasis on using robotics and sensors to quantify upper limb motor function in adults and children with brain injury or at risk for brain injury.
Rahima Mohammed - Rahima is a Senior Principal Engineer and leads the Customer Delight Office and automation infrastructure initiative of Performance, power and competitive analysis team in IAGS. Prior to this, she served as a Data Center Customer Solutions Technologist in Manufacturing Validation Engineering (MVE). Rahima led the data mining efforts on customer returned parts. She has been with Intel over 21 years after graduate schooling from Yale. Before joining MVE, she served as the advanced test module technologist in Manufacturing Development Organization (MDO). Prior to that, she served as the path finding czar for strategic emerging technologies across market segments and also setup the innovation programs for the division. Rahima led the team to deliver 15 advanced validation platform designs and pioneered innovative temperature margining thermal tools for over thirty-five silicon products.
She also chairs various technical steering committees and serves on Industry advisory boards. She demonstrates consistent leadership in IP creation, and has published 100+ papers in Intel internal and external conferences and filed 5 patents. She serves as a reviewer for various conferences like Itherm, Interpack, and a program committee member of IEEE Semi-therm conference and Burn-in-test strategies workshop. She served as the vice-program chair, program chair, and general chair of Semi-therm conferences in 2014, 2015, and 2016, respectively. She has served as the senior advisor for Women at Intel Network of Guadalajara, Mexico for the past 8 years, and a TechWomen technical mentor of 2011 and 2012. She has been working with GHC and AnitaB since 2011. She is a diversity champion, and winner 2015 SWE PRISM award.
Gerardo Bertero has worked in the digital storage industry for over 24 years. He Joined Komag, Inc. in 1994 as a principal engineer working on research and development of magnetic recording thin-film media. At Komag, he served in various management roles becoming Vice President of Sputter Research and Development in 2006. After the acquisition of Komag by Western Digital in 2007 Gerardo continued serving as Vice President of Sputter Research till 2010. From 2010 onwards, Gerardo took a position as Senior Director in the corporate CTO Office heading a team conducting advanced research in magnetic Heads, Media and Solid-State devices. Currently, Gerardo leads a team of atomistic modelers supporting advanced non-volatile memory research and oversees Western Digital’s global university research sponsorship program in the newly formed Global Technology and Strategy Office. He has 60+ peer review technical publications, has written a book chapter in magnetic recording and has given many invited talks in conferences, seminars and short courses. He served as chairperson of TMRC 2004, 2014 and will chair TMRC 2020. Gerardo has over 50 U.S. issued patents and several patent applications in process. He holds an Engineering degree from the Catholic University of Cordoba, Argentina, a Master of Science degree from Vanderbilt University and a Ph.D. degree in Materials Science and Engineering from Stanford University where he worked on Co/Pt and related metallic multilayer structures. He is a member of the IEEE Magnetics Society where he served in the Technical Advisory Committee and chair of the Santa Clara IEEE Magnetic Society Chapter. He holds an Engineering degree from the Catholic University of Cordoba, Argentina, a Master of Science degree from Vanderbilt University and a Ph.D. degree in Materials Science and Engineering from Stanford University where he worked on Co/Pt and related metallic multilayer structures. He is a member of the IEEE Magnetics Society where he served in the Technical Advisory Committee and chair of the Santa Clara IEEE Magnetic Society Chapter.
Talk: “How the RISC-V ISA is Opening Exciting Opportunities for Novel Storage and Memory Architectures” Authors: Gerardo Bertero, Ted Marena, Celeste Cooper, Richard New Astract: For many years, digital storage and system memory had few things in common coexisting separately as two necessary building blocks of traditional compute systems. With the rapid growth of NAND flash as a mass storage device and the many options available for new non-volatility in memory, while still semantically different, there is less of a clear-cut differentiation between the two. In this presentation we will make a case for why a traditionally storage-centric company sees the need to make incursions into memory, fabrics and CPU logic designs. We will discuss features of our new family of open source SweRV processors, introduce an open standard for a cache coherent memory over an ethernet fabric and time permitting will introduce a recently proposed open standard for block storage products called Zoned Storage.
Marcelo Barú is Principal E.E. at MicroSystems Engineering Inc., a Biotronik® company. As a member of the Neuro Systems & Platform Technologies, Mr. Barú is in charge of the system architecture for Biotronik’s first neuromodulation product. Mr. Barú has over 24 years of experience in the development of implantable active devices, with focus on neuromodulation, and in-vitro diagnostics. In CRM, Mr. Barú has developed electronics for pacemakers including leadless, IPGs for heart-failure treatment, and implantable biomonitors. In neuromodulation, Mr. Barú has developed IPGs for sacral roots stimulation, Peripheral Nerve Stimulation (PNS) using nerve cuff electrodes, transvenous nerve stimulation for mechanically-ventilated patients, and more recent Spinal Cord Stimulation (SCS). Mr. Barú has over 25 patents filed with half of them already granted. He holds an Electrical Engineering degree from Universidad de la República, Uruguay, and a M.A.Sc. degree from Simon Fraser University, Canada, with focus on ultra-low-power analog IC design for implantable medical applications.
Talk: “Electrochemistry of Stimulating Electrodes - Implications for Front-End System Design of Implantable Neurostimulators.” Astract: Electrical current in a metal is carried by electron flow while in tissue is carried by ion migration. At the electrode/electrolyte interface a conversion between charge-carriers occur during stimulation. Designing safe and more efficient implantable neurostimulators require basic understanding and consideration of electrochemical aspects that take place on a stimulating electrode inside the body. Further, commercial neurostimulators require meeting tight electrical requirements for market clearance and adoption. Classical circuit design approaches to meet some of these requirements (e.g. minimizing DC leakage) may force electrode potentials into regions where tissue may get damaged or electrodes dissolved. In addition, traditional “equally” charged biphasic waveforms show that the second pulse does not typically reverse the surface processes from the first pulse, because of asymmetries in the electrochemical situations under each waveform phase. This may also impact where the electrode potentials sit in steady-state compromising safety. This talk will walk through key aspects in neurostimulator front-end system design from an industry perspective, utilizing Spinal Cord Stimulation as use case but without losing generality, covering the considerations mentioned above.
LASCAS 2020 will be held at the Holiday Inn Hotel, located in the city of Escazu, west of San José.
Reservations can be made following this link. Please consider that prices listed are available until December 31st, 2019.
Please refer to the Sponsorship Guide for detailed information.