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where San José,
Costa Rica
when FEBRUARY
25 - 28, 2020

LASCAS 2020

11TH IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS

IBERCHIP PRIME-LA LAEDC

About the Event

LASCAS is the flagship conference of the IEEE Circuits and Systems Society in Latin America. Since its first edition in 2010, LASCAS provides a high-quality exchange and networking forum for researchers, professionals, and students, gathering an international audience with experts from all over the world. This event is a space where the CAS community can present new concepts and innovative approaches, learn about new trends and solutions, and receive feedback from specialists in diverse fields.

The 11th edition will take place in San José, the capital of Costa Rica. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO), where major government institutions, public universities, and industry converge in a metropolitan area with over two million people. The west urban area of San José hosts a vibrant business environment, encompassing the operation of more than 200 high-tech companies in fields such as electronics, software, and biomedical applications.

about-1

General Chairs
  • Dr. Alfonso Chacón-Rodríguez TEC, Costa Rica.
  • Dr. Renato Rimolo-Donadio TEC, Costa Rica.
Program Chairs
  • Dr. Christos Strydis Erasmus Medical Center, Netherlands.
  • Dr. Alfredo Arnaud Universidad Católica del Uruguay, Uruguay.

IBERCHIP
Technical Program Chairs
  • Dr. José Lipovetzky Universidad Nacional de Río Negro, Argentina.
  • Dr. Martín Di Federico Universidad Nacional del Sur,Argentina.
PRIME
Technical Program Chairs
  • Dr. José Lipovetzky Universidad Nacional de Río Negro, Argentina.
  • Dr. Martín Di Federico Universidad Nacional del Sur, Argentina.
Local Arrangements
Chairs
  • M.Sc. Ronny García-Ramírez TEC, Costa Rica.
  • M.Sc. Sergio Arriola-Valverde TEC, Costa Rica.
Financial
Chairs
  • M.Sc. Luis Alberto Chavarría-Zamora TEC, Costa Rica.
  • Ing. Gabriel Madrigal-Boza TEC, Costa Rica.
  • M.Sc. José Miguel Barboza-Retana TEC, Costa Rica.
Special Sessions &
Tutorials Chairs
  • Dra. Arys Carrasquilla-Batista TEC, Costa Rica.
  • M.Sc. Carlos Salazar-García TEC, Costa Rica.
Publication
Chairs
  • Dr. Carlos Meza-Benavides TEC, Costa Rica.
  • Dr. Juan José Montero TEC, Costa Rica.
Industry Liaisons
  • Eng. Luis Carlos Rosales Intel, Costa Rica.
  • M.S. José Walter Orozco HPE, Costa Rica.
  • Víctor Grimblatt Synopsys Chile R&D Center, Chile.
Publicity Chairs
  • Prof. Dr. Ricardo Reis UFRGS, Brasil

For Authors

Topics

The symposium will cover technical novelties and tutorial overviews on circuits and systems topics including but not limited to:

  • Biomedical Circuits and Systems
  • Analog and Digital Signal Processing
  • Intelligent Sensor Systems and Internet of Things
  • Nanoelectronics and Gigascale Systems
  • Electronic Design Automation
  • Circuits and Systems for Communications
  • RF Circuits and Systems
  • Smart Systems and Smart Manufacturing
  • Power Systems and Power Electronic Circuits
  • Multimedia Systems and Applications
  • Life Science Systems and Applications
  • Electronic Testing
  • Fault-Tolerant Circuits
  • Nonlinear Circuits and Systems
  • Cognitive Computing and Deep Learning
  • Computing and Big Data Applications


More Information

Please refer to the Call for Papers for detailed information.


To check or generate files with IEEE PDF eXpress please refer to: LASCAS PDF Express


Please refer to the Call for Special Sessions for detailed information.


Please refer to the Call for Demos for detailed information.


Please refer to the Call for Tutorials for detailed information.


Please refer to the Call for Papers for Iberchip for detailed information.


Please refer to the Call for Papers for PRIME-LA for detailed information.


To check or generate files with IEEE PDF eXpress please refer to: PRIME-LA PDF Express


Please refer to the Call for Papers for LAEDC for detailed information.


All the submissions are managed through Easychair, please follow these steps:

1. Log in to: EasyChair

2. Follow this link: EasyChair LASCAS2020 to access the conference submission site.


Paper Submission

Important dates for LASCAS 2020:

  • Paper submission: (last extension)
  • September 30, 2019 October 14, 2019 Due to multiple requests: October 21, 2019
  • Special session proposal:
  • October 21, 2019
  • Tutorial Proposal:
  • October 21, 2019
  • Demo Sessions:
  • October 21, 2019
  • Notification of acceptance:
  • November 18, 2019November 25, 2019
  • Camera-ready papers:
  • December 9, 2019

All papers must be uploaded using EasyChair. Please log in to EasyChair first and then click EasyChair LASCAS2020 . Papers should be presented following the IEEE Proceedings format: (download it here for MSWord) or (download it here for Latex). Papers must not exceed four pages in length. Ignore the header, and please do not number your pages. Bios and photos are not included in Conference Proceedings, thus please do not include them either. The Conference Proceedings will be submitted to the IEEE Xplore® digital library. Best papers will be invited to a special edition of the IEEE Transactions on Circuits and Systems I (TCAS-I).

Authors must transfer the copyright of their individual papers to IEEE. The authors, not IEEE, are responsible for determining whether disclosure of their material requires the prior consent of other parties and, if so, to obtain it.

15+

TOPICS

30+

SESSIONS

10+

SPEAKERS

Keynote Speakers

LASCAS 2020 gathers a remarkable group of distinguished speakers. Learn new skills and get insights from these experts from all around the world!

Academic and Industrial Invited Speakers

LASCAS 2020 gathers also a distinguished group of invited speakers from industry and academy. Learn new skills and get insights from these experts from all around the world!

Conference Schedule

The final program is now available. Download it here

13:00 - 17:00

Registration


08:30 - 10:00

Tutorial 1: Open Hardware

An Introduction to Open Source Hardware Development Leveraging Open Source Software Workflows
Diego Dompe, Laura Salazar, and José Walter Orozco. Aruba Networks. Costa Rica.
Acqua 1 Room.

In this tutorial will review the current state of the art in Open Source Hardware development, as well as discuss the challenges and potential benefits of it in academic and commercial environments. We will map learnings and methodologies from Open Source Software development into the Open Source Hardware development while providing practical examples of how to apply this knowledge.


10:00 - 10:30

Coffee Break


10:30 - 11:30

Tutorial 2: Reliability

Reliability of Nanoscale Semiconductor Devices, focusing on but not limited to Noise and Bias Temperature Instability
Gilson Wirth, Universidade Federal do Rio Grande do Sul (UFRGS), Brazil.
Acqua 1 Room.

Effects that play a major role on the reliability of today digital and analog designs are discussed, as well as effects that are expected to become relevant in future technologies. Modeling techniques to abstract the physical level effects into the design flow are studied. The main focus of the tutorial will be charge capture and emission by defects (traps) close to the Dielectric-Semiconductor interface is known to be the major source of low-frequency noise in modern MOS devices. It is also known to play a role in Bias Temperature Instability (BTI). The basics mechanisms involved in charge trapping and de-trapping will be presented, including a critical discussion of key parameters such as trapping/de-trapping time constants and the amplitude of the fluctuations induced by single traps. We introduced a new variability-based analysis, employing the autocorrelation of multiple LF-Noise spectra in terms of parameters such as frequency, bias and temperature. This technique reveals information about the mechanisms responsible for the LF-noise (and BTI) that is difficult to obtain otherwise. The talk is focused on nano scale MOS devices, but novel devices such as Resistive Switching Memory (RRAM/ReRAM) are also addressed..


13:00 - 14:30

Open Lunch Break


14:30 - 16:30

Tutorial 3: Bio-Fuell-Cell Systems

Bio-Fuel-Cell-Operated Biosensing System: Fundamental and Forecast.
Kiichi Niitsu, Nagoya University, Japan.
Acqua 1 Room.

Ensuring stable energy is one of the most important current challenges in wearable and implantable biomedical IoT systems. For addressing this issue, many developments with respect to batteries, wireless power delivery, and energy harvesting have been reported. Among them, one of the promising candidates is an introduction of bio fuel cells because it can be used as both power sources and sensing transducer. In this tutorial, the fundamental and forecast of the bio-fuel-cell-operated biosensing systems will be presented.

16:30 - 17:00

Coffee Break


17:00 - 18:30

Workshop: Aruba

ArubaCX & Network Analytics Engine: A real automated network.
José Luis Uribe, Aruba Networks.
Acqua 1 Room.

Network engineers face challenges when managing and maintaining the networks they operate. These challenges range from delivering new capabilities to ensuring the network is always available to support their business. Addressing the demands of high availability requires better visibility and tools for troubleshooting, root cause analysis and diagnostics. To meet these needs, Aruba has an industry-leading portfolio of switches for the campus network. In particular, Aruba developed the Network Analytics Engine (NAE) as part of the ArubaOS-CX network operating system. With a fully programmable and database-driven design, only ArubaOS-CX is capable of supporting the advanced visibility enabled by the NAE.

19:00 - 21:00

Welcome Cocktail


13:00 - 17:00

Registration


08:30 - 10:00

SiFive Tech Symposium


Acqua 2 Room.

• Welcome and Introduction, by Swamy Irrinki, Sr. Director of Marketing, SiFive.
• RISC-V History and State of the Union Video, by Krste Asanovic, Chairman of the RISC-V Foundation & Chief Architect at SiFive.
• Keynote: How the RISC-V ISA is Opening Exciting Opportunities, by Gerardo Bertero, CTO, Western Digital.
• Keynote: Leading the Semiconductor Design Revolution, by Swamy Irrinki, Sr. Director of Marketing, SiFive


10:00 - 10:30

Coffee Break


10:30 - 11:30

SiFive Tech Symposium


Acqua 2 Room

• RISC-V Core IP for Target Vertical Markets, by John Min, Director, FAE/CX, SiFive.
• RISC-V Software Ecosystem, by John Min, Director, FAE/CX, SiFive.
• RISC-V Core IP Debug & Bare Metal Software, by Kevin Mills, Debug & Trace Engineer, SiFive.
• SiFive University Platform, by Swamy Irrinki, Sr. Director of Marketing, SiFive.


13:00 - 14:30

Open Lunch Break


14:30 - 16:30

SiFive Tech Symposium


Acqua 2 Room

• Workshop (Laptop required): Configure Custom RISC-V Core and Bring up on FPGA, by John Min & Kevin Mills, SiFive
• Closing Remarks, by Swamy Irrinki, Sr. Director of Marketing, SiFive.

16:30 - 17:00

Coffee Break


19:00 - 21:00

Welcome Cocktail


13:00 - 17:00

Registration


08:30 - 10:00

CAS Student Chapter Activity

Design student workshop: “maximum power tracking algorithms applied to photovoltaic systems”
Terra 3 Room.

This workshop for students introduces the basic concepts that allow the design of an electronic system that works with photovoltaic cells. The main circuits that allow energy processing to meet with both objectives of obtaining the maximum amount of energy from the cells and to deliver the desired voltage and current to the load will be reviewed. Free registration, for students only.


10:00 - 10:30

Coffee Break


10:30 - 11:30

CAS Student Chapter Activity

Design student workshop: “maximum power tracking algorithms applied to photovoltaic systems”
Terra 3 Room

• This workshop for students introduces the basic concepts that allow the design of an electronic system that works with photovoltaic cells. The main circuits that allow energy processing to meet with both objectives of obtaining the maximum amount of energy from the cells and to deliver the desired voltage and current to the load will be reviewed. Free registration, for students only.


13:00 - 14:30

Open Lunch Break


14:30 - 16:30

CAS Student Chapter Activity

Design student workshop: “maximum power tracking algorithms applied to photovoltaic systems”
Terra 3 Room

This workshop for students introduces the basic concepts that allow the design of an electronic system that works with photovoltaic cells. The main circuits that allow energy processing to meet with both objectives of obtaining the maximum amount of energy from the cells and to deliver the desired voltage and current to the load will be reviewed. Free registration, for students only.

16:30 - 17:00

Coffee Break


17:00 - 18:30

CAS Student Chapter Activity

Design student workshop: “maximum power tracking algorithms applied to photovoltaic systems”
Terra 3 Room

This workshop for students introduces the basic concepts that allow the design of an electronic system that works with photovoltaic cells. The main circuits that allow energy processing to meet with both objectives of obtaining the maximum amount of energy from the cells and to deliver the desired voltage and current to the load will be reviewed. Free registration, for students only.

19:00 - 21:00

Welcome Cocktail


More information here

7:00 - 8:00

Registration


8:00 - 8:30

Opening Ceremony


Plenary Room (Acqua 1-3)
08:30 - 10:00

Special Session 1

Signal and Power Integrity
Chair: Ram Achar, Carleton University, Canada.
Plenary Room (Acqua 1-3)

SS1-1 Majid Ahadi Dolatsara and Madhavan Swaminathan. Determining worst-case eye height in low BER channels using Bayesian optimization.

SS1-2 Srinidhi Ganeshan, Naveen Kumar Elumalai, and Ramachandra Achar. A Comparative Study of MAGMA and cuBLAS Libraries for GPU based Vector Fitting.

SS1-3 Xinying Wang, Thong Nguyen, and Jose E. Schutt-Aine. PAM-4 Behavioral Modeling using Machine Learning via Laguerre-Volterra Expansion.

SS1-4 José E. Rayas-Sánchez, Francisco E. Rangel-Patiño, Benjamin Mercado-Casillas, Felipe Leal-Romo, and José L. Chávez-Hurtado. Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks.


10:00 - 10:30

Coffee Break


10:00 - 10:30

Demo Session 1

Vision systems in robotics applications
Carla Gómez Carrasquilla, David Gómez Carrasquilla and Karol Quirós Espinoza
Acqua Hall

Implementing a vision system in a robot is more probably to have an uncertain environment where all conditions could change in an instant; therefore, these systems must be flexible and adaptable to different kind of scenarios. The purpose of this demonstration is to show the audience a few tools and techniques used in vision systems and image processing to simplify some common robot tasks as shapes and color detection, distinguish between objects or analyze an object in an image. In this demo, the software used is LabVIEW by NI (National Instruments) with the platform myRIO by NI.


10:30 - 11:30

Keynote Talk

Ultra reliable low-latency communication
Vida Ilderem, VP Intel Labs
Plenary Room (Acqua 1-3)

speaker 6

5G is driving modern communications technologies to a diverse and divergent set of requirements: extreme data rates, extremely large data capacity per km2, massive machine-type communications (which require longer battery life), wider transmission areas (extend coverage in hard-to-reach regions), ultra-high density of nodes and all of this while maintaining an ultra-low latency with at least 99.999% reliability. 5G is then more evolutionary than its predecessors and is forced to leverage better and smarter use of spectrum and develop advancements in technologies like multi-antenna processing and beam management.

11:30 - 13:00

Coffee Break


13:00 - 14:00

Keynote Talk

How Auditory Cortical Representations Inspire Speech and Music Processing Systems
Shihab Shamma, University of Maryland
Plenary Room (Acqua 1-3)

speaker 2

The brain is a complex information processing system that is difficult to comprehend following any one experimental and theoretical approach. Instead, it has yielded fascinating insights only when diverse techniques were applied to its study. The remarkable capabilities of the brain has also inspired enormous interest in replicating them in Neuromorphic hardware and software so as both to derive insights into and also benefit from replicating its functionality. In this talk, I will address these topics focusing on the case of the auditory system and its applications to audio processing and recognition of speech, music, and the relevance of these applications to the understanding of language and music in the brain.

14:00 - 15:00

Keynote Talk

Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs
Jesús A. del Álamo, Massachusetts Institute of Technology
Plenary Room (Acqua 1-3)

speaker 5

In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, III-V compound semiconductors, in particular InGaAs, have received a great deal of attention as possible alternatives. Sub-10 nm CMOS applications require high-aspect ratio 3D transistors with a fin or nanowire geometry. The enhanced degree of channel charge control of advanced 3D designs allows for transistor size scaling to extremely small dimensions. At MIT, we are investigating the prospects of nanoscale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs for future logic applications. We are pursuing a top-down fabrication approach. Towards this goal, we have developed Reactive Ion Etching technology for In-containing III-V compounds that yields high aspect ratio structures with vertical and smooth sidewalls. We have also perfected digital etch to controllably thin down fins and vertical nanowires to below 10 nm width/diameter with high yield. Using these technologies, we have demonstrated InGaAs VNW MOSFETs and FinFETs with sub-10 nm critical dimensions and record electrical characteristics. More recently, we have developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We have shown that the in-situ integration of TALE with atomic layer deposition of the gate dielectric allows the fabrication of the gate stack without exposure to air. This approach has yielded the most scaled InGaAs FinFETs to date with sub-3 nm fin widths and record ON-and OFF-state characteristics. Our nanoscale device studies reveal OFF-state leakage current, mobility degradation and gate oxide trapping as major stumbling blocks for future use of InGaAs 3D transistors in logic applications. This talk will review these and other problematic issues with III-V CMOS and discuss possible solutions.

15:00 - 16:00

Coffee Break


15:00 - 16:00

Interactive Poster Session


Chair: Alfonso Chacón
Vento Hall

16:00 - 17:30

Analog and Mixed Signal Design II


Chair: Alfredo Arnaud
Plenary Room (Acqua 1-3)

17:30 - 19:00

WiCAS Event

The role of technology and robotics in global health
Chair: Arys Carrasquilla
Plenary Room (Acqua 1-3)

17:30 - 17:40, Opening: Arys Carrasquilla-Batista

17:40 - 18:20, Invited Speaker
Rahima Mohammed. Senior Principal Engineer and Customer Delight Office and Automation Infrastructure Initiative of Performance. Intel, USA
Computer evolution: Performance driven design for computing systems
Abstract: Rahima Mohammed leads the customer delight program in Intel (Santa Clara, CA), where her team builds predictive models for computer performance based on analysis of today’s devices and technologies, expected improvements moving forward, and forecasted software applications and user profiles. Based on this, Rahima’s team influences Intel’s next generation products, aiming not only to improve the technology used for manufacturing, but also to obtain more and more computing power per unit of Silicon.

18:20 – 19:00, Invited Speaker
Michelle J. Johnson, Ph.D. Assistant professor of physical medicine and rehabilitation and Assistant professor in Bioengineering. University of Pennsylvania. USA
The role of high tech robots in global health: Realistic or Not?
Abstract:
Michelle Johnson leads the Rehabilitation Robotic Research and Design Laboratory located at the Pennsylvania Institute of Rehabilitation Medicine at the University of Pennsylvania, School of Medicine. The lab is also affiliated with the General Robotics Automated Sensing Perception (GRASP) Lab. Dr. Johnson’s lab specializes in the design, development, and therapeutic use of novel, affordable, intelligent robotic assistants for rehabilitation in high and low-resource environments with an emphasis on using robotics and sensors to quantify upper limb motor function in adults and children with brain injury or at risk for brain injury.

19:00 - 21:00

WiCAS Dinner (preregistration required)


7:00 - 8:00

Registration


8:00 - 8:30

Opening Ceremony


Plenary Room (Acqua 1-3)
08:30 - 10:00

LASCAS Session

Analog and Mixed Signal Circuit Design I
Chair: Fernando Silveira
Vento 1


10:00 - 10:30

Coffee Break


10:00 - 10:30

Demo Session 1

Vision systems in robotics applications
Carla Gómez Carrasquilla, David Gómez Carrasquilla and Karol Quirós Espinoza
Acqua Hall

Implementing a vision system in a robot is more probably to have an uncertain environment where all conditions could change in an instant; therefore, these systems must be flexible and adaptable to different kind of scenarios. The purpose of this demonstration is to show the audience a few tools and techniques used in vision systems and image processing to simplify some common robot tasks as shapes and color detection, distinguish between objects or analyze an object in an image. In this demo, the software used is LabVIEW by NI (National Instruments) with the platform myRIO by NI.


10:30 - 11:30

Keynote Talk

Ultra reliable low-latency communication
Vida Ilderem, VP Intel Labs
Plenary Room (Acqua 1-3)

speaker 6

5G is driving modern communications technologies to a diverse and divergent set of requirements: extreme data rates, extremely large data capacity per km2, massive machine-type communications (which require longer battery life), wider transmission areas (extend coverage in hard-to-reach regions), ultra-high density of nodes and all of this while maintaining an ultra-low latency with at least 99.999% reliability. 5G is then more evolutionary than its predecessors and is forced to leverage better and smarter use of spectrum and develop advancements in technologies like multi-antenna processing and beam management.

11:30 - 13:00

Coffee Break


13:00 - 14:00

Keynote Talk

How Auditory Cortical Representations Inspire Speech and Music Processing Systems
Shihab Shamma, University of Maryland
Plenary Room (Acqua 1-3)

speaker 2

The brain is a complex information processing system that is difficult to comprehend following any one experimental and theoretical approach. Instead, it has yielded fascinating insights only when diverse techniques were applied to its study. The remarkable capabilities of the brain has also inspired enormous interest in replicating them in Neuromorphic hardware and software so as both to derive insights into and also benefit from replicating its functionality. In this talk, I will address these topics focusing on the case of the auditory system and its applications to audio processing and recognition of speech, music, and the relevance of these applications to the understanding of language and music in the brain.

14:00 - 15:00

Keynote Talk

Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs
Jesús A. del Álamo, Massachusetts Institute of Technology
Plenary Room (Acqua 1-3)

speaker 5

In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, III-V compound semiconductors, in particular InGaAs, have received a great deal of attention as possible alternatives. Sub-10 nm CMOS applications require high-aspect ratio 3D transistors with a fin or nanowire geometry. The enhanced degree of channel charge control of advanced 3D designs allows for transistor size scaling to extremely small dimensions. At MIT, we are investigating the prospects of nanoscale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs for future logic applications. We are pursuing a top-down fabrication approach. Towards this goal, we have developed Reactive Ion Etching technology for In-containing III-V compounds that yields high aspect ratio structures with vertical and smooth sidewalls. We have also perfected digital etch to controllably thin down fins and vertical nanowires to below 10 nm width/diameter with high yield. Using these technologies, we have demonstrated InGaAs VNW MOSFETs and FinFETs with sub-10 nm critical dimensions and record electrical characteristics. More recently, we have developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We have shown that the in-situ integration of TALE with atomic layer deposition of the gate dielectric allows the fabrication of the gate stack without exposure to air. This approach has yielded the most scaled InGaAs FinFETs to date with sub-3 nm fin widths and record ON-and OFF-state characteristics. Our nanoscale device studies reveal OFF-state leakage current, mobility degradation and gate oxide trapping as major stumbling blocks for future use of InGaAs 3D transistors in logic applications. This talk will review these and other problematic issues with III-V CMOS and discuss possible solutions.

15:00 - 16:00

Coffee Break


15:00 - 16:00

Interactive Poster Session


Chair: Alfonso Chacón
Vento Hall

16:00 - 17:30

Digital Circuits and Systems I


Chair: Ricardo Reis
Vento 1

17:30 - 19:00

WiCAS Event

The role of technology and robotics in global health
Chair: Arys Carrasquilla
Plenary Room (Acqua 1-3)

17:30 - 17:40, Opening: Arys Carrasquilla-Batista

17:40 - 18:20, Invited Speaker
Rahima Mohammed. Senior Principal Engineer and Customer Delight Office and Automation Infrastructure Initiative of Performance. Intel, USA
Computer evolution: Performance driven design for computing systems
Abstract: Rahima Mohammed leads the customer delight program in Intel (Santa Clara, CA), where her team builds predictive models for computer performance based on analysis of today’s devices and technologies, expected improvements moving forward, and forecasted software applications and user profiles. Based on this, Rahima’s team influences Intel’s next generation products, aiming not only to improve the technology used for manufacturing, but also to obtain more and more computing power per unit of Silicon.

18:20 – 19:00, Invited Speaker
Michelle J. Johnson, Ph.D. Assistant professor of physical medicine and rehabilitation and Assistant professor in Bioengineering. University of Pennsylvania. USA
The role of high tech robots in global health: Realistic or Not?
Abstract:
Michelle Johnson leads the Rehabilitation Robotic Research and Design Laboratory located at the Pennsylvania Institute of Rehabilitation Medicine at the University of Pennsylvania, School of Medicine. The lab is also affiliated with the General Robotics Automated Sensing Perception (GRASP) Lab. Dr. Johnson’s lab specializes in the design, development, and therapeutic use of novel, affordable, intelligent robotic assistants for rehabilitation in high and low-resource environments with an emphasis on using robotics and sensors to quantify upper limb motor function in adults and children with brain injury or at risk for brain injury.

19:00 - 21:00

WiCAS Dinner (preregistration required)


7:00 - 8:00

Registration


8:00 - 8:30

Opening Ceremony


Plenary Room (Acqua 1-3)
08:30 - 10:00

LASCAS Session

Imaging Techniques
Chair: Victor Grimblatt
Vento 2


10:00 - 10:30

Coffee Break


10:00 - 10:30

Demo Session 1

Vision systems in robotics applications
Carla Gómez Carrasquilla, David Gómez Carrasquilla and Karol Quirós Espinoza
Acqua Hall

Implementing a vision system in a robot is more probably to have an uncertain environment where all conditions could change in an instant; therefore, these systems must be flexible and adaptable to different kind of scenarios. The purpose of this demonstration is to show the audience a few tools and techniques used in vision systems and image processing to simplify some common robot tasks as shapes and color detection, distinguish between objects or analyze an object in an image. In this demo, the software used is LabVIEW by NI (National Instruments) with the platform myRIO by NI.


10:30 - 11:30

Keynote Talk

Ultra reliable low-latency communication
Vida Ilderem, VP Intel Labs
Plenary Room (Acqua 1-3)

speaker 6

5G is driving modern communications technologies to a diverse and divergent set of requirements: extreme data rates, extremely large data capacity per km2, massive machine-type communications (which require longer battery life), wider transmission areas (extend coverage in hard-to-reach regions), ultra-high density of nodes and all of this while maintaining an ultra-low latency with at least 99.999% reliability. 5G is then more evolutionary than its predecessors and is forced to leverage better and smarter use of spectrum and develop advancements in technologies like multi-antenna processing and beam management.

11:30 - 13:00

Coffee Break


13:00 - 14:00

Keynote Talk

How Auditory Cortical Representations Inspire Speech and Music Processing Systems
Shihab Shamma, University of Maryland
Plenary Room (Acqua 1-3)

speaker 2

The brain is a complex information processing system that is difficult to comprehend following any one experimental and theoretical approach. Instead, it has yielded fascinating insights only when diverse techniques were applied to its study. The remarkable capabilities of the brain has also inspired enormous interest in replicating them in Neuromorphic hardware and software so as both to derive insights into and also benefit from replicating its functionality. In this talk, I will address these topics focusing on the case of the auditory system and its applications to audio processing and recognition of speech, music, and the relevance of these applications to the understanding of language and music in the brain.

14:00 - 15:00

Keynote Talk

Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs
Jesús A. del Álamo, Massachusetts Institute of Technology
Plenary Room (Acqua 1-3)

speaker 5

In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, III-V compound semiconductors, in particular InGaAs, have received a great deal of attention as possible alternatives. Sub-10 nm CMOS applications require high-aspect ratio 3D transistors with a fin or nanowire geometry. The enhanced degree of channel charge control of advanced 3D designs allows for transistor size scaling to extremely small dimensions. At MIT, we are investigating the prospects of nanoscale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs for future logic applications. We are pursuing a top-down fabrication approach. Towards this goal, we have developed Reactive Ion Etching technology for In-containing III-V compounds that yields high aspect ratio structures with vertical and smooth sidewalls. We have also perfected digital etch to controllably thin down fins and vertical nanowires to below 10 nm width/diameter with high yield. Using these technologies, we have demonstrated InGaAs VNW MOSFETs and FinFETs with sub-10 nm critical dimensions and record electrical characteristics. More recently, we have developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We have shown that the in-situ integration of TALE with atomic layer deposition of the gate dielectric allows the fabrication of the gate stack without exposure to air. This approach has yielded the most scaled InGaAs FinFETs to date with sub-3 nm fin widths and record ON-and OFF-state characteristics. Our nanoscale device studies reveal OFF-state leakage current, mobility degradation and gate oxide trapping as major stumbling blocks for future use of InGaAs 3D transistors in logic applications. This talk will review these and other problematic issues with III-V CMOS and discuss possible solutions.

15:00 - 16:00

Coffee Break


15:00 - 16:00

Interactive Poster Session


Chair: Alfonso Chacón
Vento Hall

16:00 - 17:30

LASCAS Session

Sensors
Chair: Matías Miguez
Vento 2

17:30 - 19:00

LAEDC SEssion

LAEDC Session 3
Vento 2

19:00 - 21:00

WiCAS Dinner (preregistration required)


7:00 - 8:00

Registration


8:00 - 8:30

Opening Ceremony


Plenary Room (Acqua 1-3)
08:30 - 10:00

IBERCHIP Session

Iberchip Technical Session
Chair: Juan José Montero
Terra 5


10:00 - 10:30

Coffee Break


10:00 - 10:30

Demo Session 1

Vision systems in robotics applications
Carla Gómez Carrasquilla, David Gómez Carrasquilla and Karol Quirós Espinoza
Acqua Hall

Implementing a vision system in a robot is more probably to have an uncertain environment where all conditions could change in an instant; therefore, these systems must be flexible and adaptable to different kind of scenarios. The purpose of this demonstration is to show the audience a few tools and techniques used in vision systems and image processing to simplify some common robot tasks as shapes and color detection, distinguish between objects or analyze an object in an image. In this demo, the software used is LabVIEW by NI (National Instruments) with the platform myRIO by NI.


10:30 - 11:30

Keynote Talk

Ultra reliable low-latency communication
Vida Ilderem, VP Intel Labs
Plenary Room (Acqua 1-3)

speaker 6

5G is driving modern communications technologies to a diverse and divergent set of requirements: extreme data rates, extremely large data capacity per km2, massive machine-type communications (which require longer battery life), wider transmission areas (extend coverage in hard-to-reach regions), ultra-high density of nodes and all of this while maintaining an ultra-low latency with at least 99.999% reliability. 5G is then more evolutionary than its predecessors and is forced to leverage better and smarter use of spectrum and develop advancements in technologies like multi-antenna processing and beam management.

11:30 - 13:00

Coffee Break


13:00 - 14:00

Keynote Talk

How Auditory Cortical Representations Inspire Speech and Music Processing Systems
Shihab Shamma, University of Maryland
Plenary Room (Acqua 1-3)

speaker 2

The brain is a complex information processing system that is difficult to comprehend following any one experimental and theoretical approach. Instead, it has yielded fascinating insights only when diverse techniques were applied to its study. The remarkable capabilities of the brain has also inspired enormous interest in replicating them in Neuromorphic hardware and software so as both to derive insights into and also benefit from replicating its functionality. In this talk, I will address these topics focusing on the case of the auditory system and its applications to audio processing and recognition of speech, music, and the relevance of these applications to the understanding of language and music in the brain.

14:00 - 15:00

Keynote Talk

Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs
Jesús A. del Álamo, Massachusetts Institute of Technology
Plenary Room (Acqua 1-3)

speaker 5

In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, III-V compound semiconductors, in particular InGaAs, have received a great deal of attention as possible alternatives. Sub-10 nm CMOS applications require high-aspect ratio 3D transistors with a fin or nanowire geometry. The enhanced degree of channel charge control of advanced 3D designs allows for transistor size scaling to extremely small dimensions. At MIT, we are investigating the prospects of nanoscale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs for future logic applications. We are pursuing a top-down fabrication approach. Towards this goal, we have developed Reactive Ion Etching technology for In-containing III-V compounds that yields high aspect ratio structures with vertical and smooth sidewalls. We have also perfected digital etch to controllably thin down fins and vertical nanowires to below 10 nm width/diameter with high yield. Using these technologies, we have demonstrated InGaAs VNW MOSFETs and FinFETs with sub-10 nm critical dimensions and record electrical characteristics. More recently, we have developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We have shown that the in-situ integration of TALE with atomic layer deposition of the gate dielectric allows the fabrication of the gate stack without exposure to air. This approach has yielded the most scaled InGaAs FinFETs to date with sub-3 nm fin widths and record ON-and OFF-state characteristics. Our nanoscale device studies reveal OFF-state leakage current, mobility degradation and gate oxide trapping as major stumbling blocks for future use of InGaAs 3D transistors in logic applications. This talk will review these and other problematic issues with III-V CMOS and discuss possible solutions.

15:00 - 16:00

Coffee Break


15:00 - 16:00

Interactive Poster Session


Chair: Alfonso Chacón
Vento Hall

16:00 - 17:30

LASCAS Session

Digital Signal Processing
Chair: Sergio Bampi
Terra 5

17:30 - 19:00

PRIME-LA

PRIME-LA Technical Session
Chair: Renato Rimolo
Terra 5

19:00 - 21:00

WiCAS Dinner (preregistration required)


7:00 - 8:00

Registration


8:00 - 8:30

Opening Ceremony


Plenary Room (Acqua 1-3)
08:30 - 10:00

LAEDC Session

Session I
Vento 3


10:00 - 10:30

Coffee Break


10:00 - 10:30

Demo Session 1

Vision systems in robotics applications
Carla Gómez Carrasquilla, David Gómez Carrasquilla and Karol Quirós Espinoza
Acqua Hall

Implementing a vision system in a robot is more probably to have an uncertain environment where all conditions could change in an instant; therefore, these systems must be flexible and adaptable to different kind of scenarios. The purpose of this demonstration is to show the audience a few tools and techniques used in vision systems and image processing to simplify some common robot tasks as shapes and color detection, distinguish between objects or analyze an object in an image. In this demo, the software used is LabVIEW by NI (National Instruments) with the platform myRIO by NI.


10:30 - 11:30

Keynote Talk

Ultra reliable low-latency communication
Vida Ilderem, VP Intel Labs
Plenary Room (Acqua 1-3)

speaker 6

5G is driving modern communications technologies to a diverse and divergent set of requirements: extreme data rates, extremely large data capacity per km2, massive machine-type communications (which require longer battery life), wider transmission areas (extend coverage in hard-to-reach regions), ultra-high density of nodes and all of this while maintaining an ultra-low latency with at least 99.999% reliability. 5G is then more evolutionary than its predecessors and is forced to leverage better and smarter use of spectrum and develop advancements in technologies like multi-antenna processing and beam management.

11:30 - 13:00

Coffee Break


13:00 - 14:00

Keynote Talk

How Auditory Cortical Representations Inspire Speech and Music Processing Systems
Shihab Shamma, University of Maryland
Plenary Room (Acqua 1-3)

speaker 2

The brain is a complex information processing system that is difficult to comprehend following any one experimental and theoretical approach. Instead, it has yielded fascinating insights only when diverse techniques were applied to its study. The remarkable capabilities of the brain has also inspired enormous interest in replicating them in Neuromorphic hardware and software so as both to derive insights into and also benefit from replicating its functionality. In this talk, I will address these topics focusing on the case of the auditory system and its applications to audio processing and recognition of speech, music, and the relevance of these applications to the understanding of language and music in the brain.

14:00 - 15:00

Keynote Talk

Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs
Jesús A. del Álamo, Massachusetts Institute of Technology
Plenary Room (Acqua 1-3)

speaker 5

In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, III-V compound semiconductors, in particular InGaAs, have received a great deal of attention as possible alternatives. Sub-10 nm CMOS applications require high-aspect ratio 3D transistors with a fin or nanowire geometry. The enhanced degree of channel charge control of advanced 3D designs allows for transistor size scaling to extremely small dimensions. At MIT, we are investigating the prospects of nanoscale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs for future logic applications. We are pursuing a top-down fabrication approach. Towards this goal, we have developed Reactive Ion Etching technology for In-containing III-V compounds that yields high aspect ratio structures with vertical and smooth sidewalls. We have also perfected digital etch to controllably thin down fins and vertical nanowires to below 10 nm width/diameter with high yield. Using these technologies, we have demonstrated InGaAs VNW MOSFETs and FinFETs with sub-10 nm critical dimensions and record electrical characteristics. More recently, we have developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We have shown that the in-situ integration of TALE with atomic layer deposition of the gate dielectric allows the fabrication of the gate stack without exposure to air. This approach has yielded the most scaled InGaAs FinFETs to date with sub-3 nm fin widths and record ON-and OFF-state characteristics. Our nanoscale device studies reveal OFF-state leakage current, mobility degradation and gate oxide trapping as major stumbling blocks for future use of InGaAs 3D transistors in logic applications. This talk will review these and other problematic issues with III-V CMOS and discuss possible solutions.

15:00 - 16:00

Coffee Break


15:00 - 16:00

LAEDC Session

Flash Poster Session
Vento 3

16:00 - 17:30

LAEDC Session

Session II
Vento 3

17:30 - 19:00

LAEDC Session

Session IV
Vento 3

19:00 - 21:00

LAEDC Cocktail (preregistration required)


08:30 - 10:00

Special Session 2

REHAB-CAS: Affordable Technology Systems for Rehabilitation in Low and Middle-Income Countries
Chair: Michelle Johnson. University of Pennsylvania.
Plenary Room (Acqua 1-3)

Designing effective rehabilitation engineering systems are important solutions in the fight to reduce healthcare disparities in rehabilitation. To be effective we must envision innovative ways of developing and using rehabilitation technologies for rehabilitation care in low and middle-income countries. This workshop highlights the need and some of these innovations. It will help the CAS community to understand the need and use of engineering systems within the rehabilitation context.

SS2-1 Beatriz Coto-Solano. Challenges in the Incorporation of Rehabilitation Technology to Public Health in Costa Rica.

SS2-2 Samuel Gaardsmoe, Maria Ovando, Kevin Bui, and Michelle J. Johnson. Development of a low-cost balance assessment system for use in an affordable robot gym in low and middle income countries.

SS2-3 Karla J. Bustamante Valles, Daniel Comaduran, Marquez, and Michelle J. Johnson. Robotic Rehabilitation Therapy in Chihuahua Mexico, challenges from translating a clinical research protocol to clinical practice.

SS2-4 Verónica Valverde-Arredondo and Arys Carrasquilla-Batista. Haptic system for upper limb rehabilitation with hand grip strength measurements and Internet of Things capabilities.

SS2-5 Carla Gomez-Carrasquilla, Karol Quiros-Espinoza, and Arys Carrasquilla-Batista. Wheelchair control through eye blinking and IoT platform.


10:00 - 10:30

Coffee Break


10:00 - 10:30

Demo Session 1

Haptic system for upper limb rehabilitation with hand grip strength measurements and Internet of Things capabilities.
Verónica Valverde Arredondo and Arys Carrasquilla Batista
Acqua Hall

This demo describes the design process of a haptic system that is able to measure hand strength, perform rehabilitation exercises for the upper limbs and has Internet of Things capabilities. A functional prototype was built using 3D printing along with an existing haptic controller and is used as a demo. The programming was coded in Python and the data was sent to an IoT platform for visualization and control. In addition, tests were carried out to determine the error in the measurements and the data communication between each device.


10:30 - 11:30

Keynote Talk

Overview of 5G Radio Systems, Requirements, Challenges, and Research Areas.
Sayfe Kiaei, Arizona State University.
Plenary Room (Acqua 1-3)

speaker 4

As demand grows for wireless connectivity in many applications including autonomous vehicles, artificial intelligence, telemedicine and virtual reality will have a dominate role in 5G. 5G will be delivering higher data throughput, extremely low latency and speeds up to 100 times faster than 4G. This talk will give an overview of the 5G technology, standards, and challenges for RF and wireless transceivers. The talk will focus on the RF architecture and transceivers for the 5G RF front-end.

11:30 - 13:00

Lunch Break


13:00 - 14:00

Keynote Talk

Energy-Scalable Many-Core Servers: Follow your Brain!
David Atienza, École polytechnique fédérale de Lausanne (EPFL)
Plenary Room (Acqua 1-3)

speaker 7

Continuous advances in manufacturing technologies are enabling the development of more powerful and compact high-performance computing (HPC) servers made of many-core processing architectures. However, this soaring demand for computing power in the last years has grown faster than semiconductor technology evolution can sustain, and has produced as collateral undesirable effect a surge in power consumption and heat density in these new HPC servers, which result on significant performance degradation. In this talk, Prof. Atienza will advocate to completely revise the current practices to design HPC server architectures. In particular, inspired by the mammalian brain, I propose to design a disruptive three-dimensional (3D) computing server architecture that overcomes the prevailing worst-case power and cooling provisioning paradigm for servers. This new 3D server design champions a new system-level thermal modeling and machine learning based task assignment (developed in cooperation with Facebook), which can be used by novel proactive energy controllers for detailed heat and energy management in many-core HPC servers, thanks to micro-scale liquid cooling. Then, it will be shown the impact of new near-threshold computing architectures on many-core server design. Finally, I will explain how we can integrate new on-chip microfluidic fuel cell networks to enable energy-scalability in future generations of many-core HPC servers targeting the next-generation of Exascale computing, thanks to the new PowerCool and Gem5-X open-source multi-core architectural simulators.

14:00 - 14:45

Invited Speaker

Memory-Driven Computing.
Kevin Boyum, HPE Silicon Design Lab, USA
Plenary Room (Acqua 1-3)

speaker 2is

Big Data is here, growing, and sourcing tremendous unrealized business opportunities! Yet, as the number of data sources and the amount of data gathered continues to increase exponentially, transistor scaling and the corresponding increase in compute ability has slowed dramatically, reducing our ability to interact with this mounting data in a meaningful timeframe. Hewlett Packard Enterprise has met this challenge with an entirely new approach called Memory-Driven Computing. Designed specifically for Big Data, Memory-Driven Computing turns traditional computer architecture on its head by making memory central to the system, rather than processors. This presentation explores the fundamental principles and building blocks of Memory-Driven Computing and how it differs from conventional design, then highlights examples of the incredible speedups achieved so far on real-world workloads.

14:45 - 15:30

Invited Speaker

How the RISC-V ISA is Opening Exciting Opportunities for Novel Storage and Memory Architectures
Gerardo Bertero, CTO Western Digital, USA
Plenary Room (Acqua 1-3)

speaker 5is

For many years, digital storage and system memory had few things in common coexisting separately as two necessary building blocks of traditional compute systems. With the rapid growth of NAND flash as a mass storage device and the many options available for new non-volatility in memory, while still semantically different, there is less of a clear-cut differentiation between the two. In this presentation, we will make a case for why a traditionally storage-centric company sees the need to make incursions into memory, fabrics and CPU logic designs. We will discuss features of our new family of open source SweRV processors, introduce an open standard for a cache coherent memory over an Ethernet fabric and time permitting will introduce a recently proposed open standard for block storage products called Zoned Storage.

15:30 - 16:00

Coffee Break


16:00 - 17:30

Industrial Forum

from Multinational to Local Industrial Ecosystems
Moderator: Victor Grimblatt
Plenary Room (Acqua 1-3)

Panel:
• Ileana Rojas, Gerente General Componentes Intel Costa Rica.
• Antonio Collantes, Gerente General de HPE Costa Rica.
• Vannesa Gibson, Head of Investment Climate, CINDE, Costa Rica.
• Alfredo Arnaud, BQN, Uruguay.
• Javier Carvajal, ImagineXYZ, Costa Rica.

17:30 - 22:00

Gala Dinner

Gran Hotel Costa Rica, Curio Collection by Hilton
Departure from Hotel Holiday-Inn
San José Downtown

08:30 - 10:00

Special Session 3

Neurotechnology, Circuits and Systems Design Challenges
Chairs: Tim Constandinou, Imperial College, United Kingdom. Dr. Fernando Silveira. Universidad de la República, Uruguay.
Plenary Room (Acqua 1-3)

The advances in the understanding and capabilities for interacting fluently with the nervous system of humans in particular and animals in general, known as neurotechnology, opens enormous opportunities for medical applications. It may also enable new ways for humans to interact and take advantage of information technology. The fulfillment of these promises needs multiple advances the CAS domains. In this special session aspects related to the sensing (neural amplifiers) and the actuation (stimulation) as well as general system design issues (power management and safety) will be covered.

SS3-1 Alfredo Arnaud and Matías Miguez. Stacking Multiple Differential Pairs for a NEF lower than 1 Amplifier aimed at Electroneurographic Signal Recording.

SS3-2 Rui Guan, Pedro G. Zufiria, Vasiliki Giagka, and Wouter A. Serdijn. Circuit Design Considerations for Power-Efficient and Safe Implantable Electrical Neurostimulators.

SS3-3 Dorian Haci, Yan Liu, Sara S. Ghoreishizadeh, and Timothy G. Constandinou. Key Considerations for Power Management in Active Implantable Medical Devices.

SS3-4 Renzo Caballero, Gonzalo Carozo, María C. Costa-Rauschert, Pablo Aguirre, Conrado Rossi-Aicardi, and Julián Oreggioni. Biopotential integrated preamplifier.


10:00 - 10:30

Coffee Break


10:00 - 10:30

Demo Session 3

Maker prototyping techniques for a development a low cost electrospinning machine
Javier Carvajal Artavia, Bryan Salazar Ramírez and Hugo Sánchez Ortiz
Acqua Hall

Electrospinning fiber production is a well-studied method to create nanofibers by electrical forces. Depending on their chemical, physical and mechanical characteristics, they have a wide range of applications as: medicals applications, polymers for batteries, textile industry and others. However, the actual cost for the machine to create these fibers is high, making the acquisition of this equipment complicated for experimentation. This demo will present the application of Maker prototyping techniques for the development of a low cost electrospinning machine that operates between 5kV and 30kV, designed and fabricated by the company ImagineXYZ.


10:30 - 11:30

Keynote Talk

Artificial Neural Networks for EMC Engineering.
Christian Schuster, Hamburg University of Technology, Germany.
Plenary Room (Acqua 1-3)

speaker 1

Artificial Neural Networks – in short: ANNs – are one of the many methods used nowadays in Machine Learning (ML). Their fundamental development has spanned many decades and they have found widespread use in such areas as image and speech recognition as well as autonomous driving. Despite this success, ANNs have not been applied routinely to complex engineering task such as guaranteeing the Electromagnetic Compatibility (EMC) of electrical and electronic components and systems. In this talk – a after a short, layman’s introduction into ML and ANNs – we will look in some detail at the current state of art in the application of ANNs to EMC engineering including an example from power delivery network design that we worked recently on at TUHH. A personal outlook will conclude the presentation.

11:30 - 13:00

Lunch Break


13:00 - 14:00

Keynote Talk

The Medicine of the Future You'll Take Only Once, and it is Bioelectronic.
Wouter Serdjin, Delft University of Technology, The Netherlands
Plenary Room (Acqua 1-3)

speaker 3

The 21st century will be the century in which we will unravel the intricacies of the brain and the rest of our nervous system and in which we will learn how to interact with our electrochemical mainframe better by means of electricity, light or ultrasound. Tiny electronic devices will give us back lost senses, lost control, bypass lesions and treat an unprecedented range of brain disorders, thereby bringing back quality of life to the deaf, the blind, the paralyzed and the mentally disturbed. This talk will address how these ‘bioelectronic medicines’ do this, what they look like and which future circuit and system developments are needed to make them a reality. We will discuss their constraints on size, their energy challenge, their adherence to the body and their security aspects. We will also discuss how to make them truly personalized, so that they gracefully adapt to your therapeutic needs and you truly will feel better.

14:00 - 14:45

Invited Speaker

An approach to generational, pre-silicon SoC/ASIC Prototyping
Naysen Robertson, HPE Silicon Design Lab, USA
Plenary Room (Acqua 1-3)

speaker 1is

A majority of organizations developing application-specific integrated circuit (ASIC) designs rely upon some form of pre-silicon hardware to accelerate verification of their solutions beyond software based simulation/emulation. Software simulation of silicon design is flexible and relatively low-cost, but executing micro-code and long dwell simulation is time-prohibitive and incapable of capturing the parallel nature of synchronous designs. This leads to verification misses at synchronization thresholds and other temporal flaws introduced in the register transfer level (RTL) model. There is a continuum of hardware-based Design Verification solutions that ranges from simple, off-the-shelf printed circuit assembly (PCA) cards with a programmable device to the high-cost, high-complexity emulation boxes available from our premier Electronic Design Automation (EDA) vendors. At HPE, our approach to enabling an ASIC equivalent prototyping solution that is cost, effort, and capability optimized involves the use of generational, custom, field programmable gate array (FPGA)-based PCAs designed to load our Baseboard Management Controller (BMC) ASIC design, execute WiP Firmware, and integrate within current generation server platforms that are modified to detect and seamlessly connect previous or current generation ASIC }add-in cards as well as next-generation FPGA-based cards to the host system. This presentation gives an overview of this approach to FPGA accelerated ASIC validation with an analysis of the trade-offs with alternative approaches.

14:45 - 15:30

Invited Speaker

Electrochemistry of Stimulating Electrodes - Implications for Front-End System Design of Implantable Neurostimulators
Marcelo Barú, Principal EE of Biotronik.
Plenary Room (Acqua 1-3)

speaker 6is

Electrical current in a metal is carried by electron flow while in tissue is carried by ion migration. At the electrode/electrolyte interface a conversion between charge-carriers occurs during stimulation. Designing safe and more efficient implantable neurostimulators requires basic understanding and consideration of electrochemical aspects that take place on a stimulating electrode inside the body. Further, commercial neurostimulators shall meet tight electrical requirements for market clearance and adoption. Classical circuit design approaches to fulfill some of these requirements (e.g. minimizing DC leakage) may force electrode potentials into regions where tissue may get damaged or electrodes dissolved. In addition, traditional “equally” charged biphasic waveforms show that the second pulse does not typically reverse the surface processes from the first pulse, given asymmetries in the electrochemical situations under each waveform phase. This may also impact where the electrode potentials sit in steady-state compromising safety. This talk will walk through key aspects in neurostimulator front-end system design from an industry perspective, utilizing Spinal Cord Stimulation as use case but without losing generality, covering the considerations mentioned above.

15:30 - 16:00

Coffee Break


16:00 - 17:30

Special Session 4

IoT in Agribusiness
Chair: Victor Grimblatt
Plenary Room (Acqua 1-3)

World population is growing; global population in 2050 will exceed 10 billion people. As population growth, cities are also growing, so the total arable land in the world is decreasing. However, per FAO (Food and Agriculture Organization of the United Nations), current agricultural production should be increased by 70% by 2050. FAO is also estimating that, to date, 75% of the varieties of agricultural crops have been lost and that three quarters of the world’s food supply depend on just 12 species of plants and five species of animals. On the other hand, agricultural production is the cause of 69% of water consumption and it is estimated to increase by 19% by 2050. Global warming is also not helping to this difficult scenario. This challenging scenario can only be addressed using technology, especially IoT in the food domain. Application such as food transportation, food processing, food analysis, smart agriculture, cattle breeding, food improvement through genetics are just some examples of how technology is addressing the challenges associated to food.

SS4-1 Laura Hernández-Alpizar, Arys Carrasquilla-Batista, and Lilliana Sancho-Chavarría. IoT application for water quality monitoring: nitrates.

SS4-2 Alfredo Arnaud and Guillermo Costa. Ultra low-cost sensors using RFID standards for data collection, for IoT systems in food production and logistics.

SS4-3 Carlos Muñoz, Juan Huircan, Fernando Huenupan, and Pedro Cachaña. PTZ camera tuning for real time monitoring of cows in grazing fields.

SS4-4 Victor Grimblatt. IoT for Agribusiness: An Overview.

17:30 - 18:00

Closing

Best Paper Award and Closing Ceremony
Plenary Room (Acqua 1-3)

Registration

LASCAS 2020 registration site is open now!
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    About Costa Rica

    The 11th edition will take place in San José, the capital of Costa Rica. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO) .

    Venue

    LASCAS 2020 will be held at the Holiday Inn Hotel, located in the city of Escazu, west of San José.

    Reservations can be made following this link. Please consider that prices listed are available until December 31st, 2019.

    A Taxi service from the Airport to the Venue costs $25-$30 depending on traffic conditions. Official airport taxi services and reservations can be explored using this link.

    Refer to the following sites for country information and tourist information

    Sponsors & Partners

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    Conference Contacts

    More Information
    General Chairs
    • Dr. Alfonso Chacón-Rodríguez Instituto Tecnológico de Costa Rica, Costa Rica. alchacon@tec.ac.cr
    • Dr. Renato Rimolo-Donadio Instituto Tecnológico de Costa Rica, Costa Rica. rrimolo@tec.ac.cr
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    lascas2020
    11th IEEE Latin American Symposium on Circuits and Systems
    IEEE Circuits and Systems Society, Costa Rica Chapter, costarica-cas{at}ieee.org
    A not-for-profit organization, IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity.