11TH IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS
San José, Costa Rica
February 26-28, 2020
The Iberchip workshop provides an annual forum to academic and industrial researchers from Iberoamerican countries in which to exchange experiences, share knowledge, and establish relations to foster the development of activities related to the field of microelectronics. Special emphasis is put in the improvement of education and training, and in the promotion of joint cooperative projects.
The 26th edition will take place in San José, the capital of Costa Rica. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO), where major government institutions, public universities, and industry converge in a metropolitan area with over two million people. The west urban area of San José hosts a vibrant business environment, encompassing the operation of more than 200 high-tech companies in fields such as electronics, software, and biomedical applications.Call For Papers
San José, Costa Rica
February 26-28, 2020
The PhD Research in Microelectronics and Electronics Conference in Latin America (PRIME-LA) is a conference where PhD students and post-docs with less than one-year post-PhD experience can present their research results and network with experts from industry, academia and research.
The third edition will take place in San José, the capital of Costa Rica. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO), where major government institutions, public universities, and industry converge in a metropolitan area with over two million people. The west urban area of San José hosts a vibrant business environment, encompassing the operation of more than 200 high-tech companies in fields such as electronics, software, and biomedical applications.Call For Papers
LASCAS is the flagship conference of the IEEE Circuits and Systems
Society in Latin America. Since its first edition in 2010, LASCAS provides a high-quality exchange
and networking forum for researchers, professionals, and students, gathering an international
audience with experts from all over the world. This event is a space where the CAS community can
present new concepts and innovative approaches, learn about new trends and solutions, and receive
feedback from specialists in diverse fields.
The 11th edition will take place in San José, the capital of Costa Rica. The city is located in the central region of the country, a strategic place nearby the Juan Santamaría International Airport (SJO), where major government institutions, public universities, and industry converge in a metropolitan area with over two million people. The west urban area of San José hosts a vibrant business environment, encompassing the operation of more than 200 high-tech companies in fields such as electronics, software, and biomedical applications.
Christian Schuster (S'98 - M'00 - SM'05) received the Diploma degree in physics from the University of Konstanz, Germany, in 1996, and the Ph. D. degree in electrical engineering from the Swiss Federal Institute of Technology (ETH), Zurich, Switzerland, in 2000. Since 2006 he is full professor and head of the Institute of Electromagnetic Theory at the Hamburg University of Technology (TUHH), Germany. Prior to that he was with the IBM T. J. Watson Research Center, Yorktown Heights, NY, where he was involved in high-speed optoelectronic package and backplane interconnect modeling and signal integrity design for new server generations. His currents interests include signal and power integrity of digital systems, multiport measurement and calibration techniques, and development of electromagnetic simulation methods for communication electronics.
Dr. Schuster received IEEE Transactions on EMC Best Paper Awards in 2001 and 2015, IEEE Transactions on CPMT Best Paper Awards in 2012 and 2016, IEC DesignCon Paper Awards in 2005, 2006, 2010, 2017 and 2018, three IBM Research Division Awards between 2003 and 2005, and IBM Faculty Awards in 2009 and 2010. He is a member of the German Physical Society (DPG) and several technical program committees of international conferences on signal and power integrity, and electromagnetic compatibility. He was serving as a Distinguished Lecturer for the IEEE EMC Society in the period 2012-2013, as a member of the Board of Directors of the EMC Society in 2015, and is currently chair of the German IEEE EMC Chapter and Associate Editor for the IEEE Transactions on EMC.
Dr. Shamma's research deals with issues in cognitive neuroscience, computational neuroscience, neuromorphic engineering, and the development of microsensor systems for experimental research and neural prostheses. Primary focus has been on studying the principles underlying the processing and recognition of complex sounds (speech and music) in the auditory system, and specifically the role of attention and rapid plasticity in facilitating these functions. Research projects involve single-unit behavioral neurophysiology and 2-photon imaging of the auditory cortex, and its interactions with higher cortical centers such as the prefrontal cortex and secondary auditory areas. Signal processing algorithms inspired by these experiments are developed and applied in a variety of systems such as speech and voice recognition, diagnostics in industrial manufacturing, and underwater acoustics.
Other research interests include the development of microelectrode arrays for recording and stimulation of neural signals, analog VLSI implementations of auditory processing algorithms, and development of robotic systems for the detection and tracking of multiple simultaneous sound sources.
Wouter A. Serdijn (M'98, SM'08, F'11) was born in Zoetermeer ('Sweet Lake City'), the Netherlands, in 1966. He received the M.Sc. (cum laude) and Ph.D. degrees from Delft University of Technology, Delft, The Netherlands, in 1989 and 1994, respectively. Currently, he is a full professor in bioelectronics at Delft University of Technology, where he heads the Section Bioelectronics, and a visiting honorary professor at University College London, in the Analog and Biomedical Electronics group. His research interests include integrated biomedical circuits and systems for biosignal conditioning and detection, neuroprosthetics, transcutaneous wireless communication, power management and energy harvesting as applied in, e.g., hearing instruments, cardiac pacemakers, cochlear implants, neurostimulators, portable, wearable, implantable and injectable medical devices and electroceuticals.
He is co-editor and co-author of the books Analog IC Design Techniques for Nanopower Biomedical Signal Processing (River Publishers 2016), Design of Efficient and Safe Neural Stimulators - a multidisciplinary approach (Springer, 2016), EMI-Resilient Amplifier Circuits (Springer 2013), Ultra Low-Power Biomedical Signal Processing: an analog wavelet filter approach for pacemakers (Springer, 2009), Circuits and Systems for Future Generations of Wireless Communications (Springer, 2009), Power Aware Architecting for data dominated applications (Springer, 2007), Adaptive Low-Power Circuits for Wireless Communications (Springer, 2006), Research Perspectives on Dynamic Translinear and Log-Domain Circuits (Kluwer, 2000), Dynamic Translinear and Log-Domain Circuits (Kluwer, 1998) and Low-Voltage Low-Power Analog Integrated Circuits (Kluwer, 1995). He authored and co-authored 8 book chapters, 4 patents and more than 300 scientific publications and presentations. He teaches Circuit Theory, Analog Integrated Circuit Design, Analog CMOS Filter Design, Active Implantable Biomedical Microsystems and Bioelectronics. He received the Electrical Engineering Best Teacher Award in 2001, in 2004 and in 2015. He has served, a.o., as General Co-Chair for IEEE ISCAS 2015 and for IEEE BioCAS 2013, Technical Program Chair for IEEE BioCAS 2010 and for IEEE ISCAS 2010, 2012 and 2014, as a member of the Board of Governors (BoG) of the IEEE Circuits and Systems Society ( 2006—2011), as chair of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems society, and as Editor-in-Chief for IEEE Transactions on Circuits and Systems—I: Regular Papers (2010—2011). Currently, he is the chair of the Steering Committee and an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems (T-BioCAS). Wouter A. Serdijn is an IEEE Fellow, an IEEE Distinguished Lecturer and a mentor of the IEEE. In 2016, he received the IEEE Circuits and Systems Society Meritorious Service Award.
Motorola Endowed Professor in Integrated Circuits. Director, USAID PCASE Center on Energy. Director, NSF Connection One Center. Professor, School of Electrical, Computer, and Energy Engineering Ira. A. Fulton Schools of Engineering, Arizona State University Ph.D., electrical and computer engineering, Washington State University, 1987. Dr. Kiaei has been with ASU since January 2001. He is a professor and Motorola Endowed professor and chair in analog and RF integrated circuits. He is the director of the USAID-funded U.S.A & Pakistan Centers for Advanced Studies in Energy program (USPCAS-E (https://uspcase.asu.edu/). He is also the director of NSF Connection One research center with a focus on integrated communication system. Dr. Kiaei was the associate dean of research at the Ira A. Fulton Schools of Engineering from 2009 to 2102. From 1993 to 2001, he was a senior member of technical staff with the Wireless Technology Center and Broadband Operations at Motorola where he was responsible for the development of RF and transceiver integrated circuits, GPS RF IC and digital subscriber lines (DSL) transceivers. Kiaei was an associate professor at Oregon State University from 1987 to 1993. He was the co-director of the industry-university center for the Design of Analog/Digital ICs (CDADIC).
He has published over 150 journal and conference papers and holds several patents. His academic and research interests are in Energy, wireless system (1G to 5G), RF, and Mixed-Signal. His research projects are funded by a large number of industrial sponsors and federal funding agencies. Dr. Kiaei is an IEEE Fellow, and has been the chair and on the technical program committee of several IEEE conferences including RFIC, MTT, ISCAS and other international conferences.
Jesús A. del Alamo is Professor of Electrical Engineering and Director of the Microsystems Technology Laboratories at Massachusetts Institute of Technology. He obtained a Telecommunications Engineer degree from the Polytechnic University of Madrid and MS and PhD degrees in Electrical Engineering from Stanford University. From 1985 to 1988 he was with NTT LSI Laboratories in Atsugi (Japan) and since 1988 he has been with the Department of Electrical Engineering and Computer Science of MIT where he is at the present time the Donner Professor. His current research interests are centered on nanoelectronics based on compound semiconductors for future logic, communications and power management applications. Prof. del Alamo was an NSF Presidential Young Investigator. He is a member of the Royal Spanish Academy of Engineering and Fellow of the IEEE and the APS. He has received the Intel Outstanding Researcher Award, the SRC Technical Excellence Award, and the IEEE EDS Education Award. He currently serves as Editor-in-Chief of IEEE Electron Device Letters.
Talk: Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs.In the last few years, as Si electronics faces mounting difficulties to maintain its historical scaling path, III-V compound semiconductors, in particular InGaAs, have received a great deal of attention as possible alternatives. Sub-10 nm CMOS applications require high-aspect ratio 3D transistors with a fin or nanowire geometry. The enhanced degree of channel charge control of advanced 3D designs allows for transistor size scaling to extremely small dimensions. At MIT, we are investigating the prospects of nanoscale InGaAs FinFETs and vertical nanowire (VNW) MOSFETs for future logic applications. We are pursuing a top-down fabrication approach. Towards this goal, we have developed Reactive Ion Etching technology for In-containing III-V compounds that yields high aspect ratio structures with vertical and smooth sidewalls. We have also perfected digital etch to controllably thin down fins and vertical nanowires to below 10 nm width/diameter with high yield. Using these technologies, we have demonstrated InGaAs VNW MOSFETs and FinFETs with sub-10 nm critical dimensions and record electrical characteristics. More recently, we have developed thermal atomic-layer etching (TALE) for InGaAs and InAlAs. We have shown that the in-situ integration of TALE with atomic layer deposition of the gate dielectric allows the fabrication of the gate stack without exposure to air. This approach has yielded the most scaled InGaAs FinFETs to date with sub-3 nm fin widths and record ON-and OFF-state characteristics. Our nanoscale device studies reveal OFF-state leakage current, mobility degradation and gate oxide trapping as major stumbling blocks for future use of InGaAs 3D transistors in logic applications. This talk will review these and other problematic issues with III-V CMOS and discuss possible solutions.
Naysen Robertson began his career in the Business Critical Systems unit at HP in 1999. Working as a hardware engineer and later architect, Naysen's technical leadership helped deliver several Itanium and x86 enterprise-class systems, such as the award winning ProLiant DL980 scale-up, 8-skt server. Naysen currently serves as a Master technologist in the HPE Silicon Design Lab where he is sought after for his broad expertise in systems architecture and his deep knowledge in the field of FPGA design and ASIC emulation. He synthesizes his experience, skillsets and leadership to solve the pressing challenges of pre-silicon design validation. Naysen has a BS in CPE from California State University of Sacramento, and he holds several patents in areas such as NUMA architecture and embedded system manageability.
Talk: An approach to generational, pre-silicon SoC/ASIC Prototyping Abstract: A majority of organizations developing application-specific integrated circuit (ASIC) designs rely upon some form of pre-silicon hardware to accelerate verification of their solutions beyond software based simulation/emulation. Software simulation of silicon design is flexible and relatively low-cost, but executing micro-code and long dwell simulation is time-prohibitive and incapable of capturing the parallel nature of synchronous designs. This leads to verification misses at synchronization thresholds and other temporal flaws introduced in the register transfer level (RTL) model. There is a continuum of hardware-based Design Verification solutions that ranges from simple, off-the-shelf printed circuit assembly (PCA) cards with a programmable device to the high-cost, high-complexity emulation boxes available from our premier Electronic Design Automation (EDA) vendors. At HPE, our approach to enabling an ASIC equivalent prototyping solution that is cost, effort, and capability optimized involves the use of generational, custom, field programmable gate array (FPGA)-based PCAs designed to load our Baseboard Management Controller (BMC) ASIC design, execute WiP Firmware, and integrate within current generation server platforms that are modified to detect and seamlessly connect previous or current generation ASIC }add-in cards as well as next-generation FPGA-based cards to the host system. This presentation gives an overview of this approach to FPGA accelerated ASIC validation with an analysis of the trade-offs with alternative approaches.
Kevin Boyum received his BSEE degree from the Virginia Military Institute in 1989 and his MSEE degree from the Air Force Institute of Technology in 1993, and served as an Electrical Engineer performing research and development in the United States Air Force from 1989 through 1996. Joining Hewlett Packard's Enterprise Server and Technology Lab in 1997, he developed state of the art data capture hardware for the jointly developed HP / Intel Itanium processor chipset and then architected management and storage solutions for HP's Itanium-based servers and for HPE's Synergy platform. In 2015 Kevin was selected as the hardware engineering lead for HP Labs' project The Machine, HP's first prototype for the Memory Driven Compute architecture, and following the successful technology demonstration has continued as a systems architect in HPE's Silicon Design Lab. Kevin has authored and co-authored 10 patents and his profession interests include embedded systems design and programming, computer systems architecture, and machine learning.
Talk: Memory-Driven Computing. Big Data is here, growing, and sourcing tremendous unrealized business opportunities! Yet, as the number of data sources and the amount of data gathered continues to increase exponentially, transistor scaling and the corresponding increase in compute ability has slowed dramatically, reducing our ability to interact with this mounting data in a meaningful timeframe. Hewlett Packard Enterprise has met this challenge with an entirely new approach called Memory-Driven Computing. Designed specifically for Big Data, Memory-Driven Computing turns traditional computer architecture on its head by making memory central to the system, rather than processors. This presentation explores the fundamental principles and building blocks of Memory-Driven Computing and how it differs from conventional design, then highlights examples of the incredible speedups achieved so far on real-world workloads.
LASCAS 2020 will be held at the Holiday Inn Hotel, located in the city of Escazu, west of San José.
Reservations can be made following this link. Please consider that prices listed are available until December 31st, 2019.
Please refer to the Sponsorship Guide for detailed information.